1.1 This guide strictly applies only to the exposure of unbiased silicon (Si) or gallium arsenide (GaAs) semiconductor components (integrated circuits, transistors, and diodes) to neutron radiation to determine the permanent displacement damage in the components. Validated 1-MeV displacement damage functions codified in national standards, for example Practice E722, for silicon and GaAs are not currently standardized for other semiconductor materials. 1.2 Elements of this guide, with the deviations noted, may also be applicable to the exposure of semiconductors comprised of other materials, for example Ge, GaN, SiC, or AlN, except that validated 1-MeV displacement damage functions, codified in national standards, are not currently available. 1.3 Only the conditions of exposure are addressed in this guide. The effects of radiation on the test sample should be determined using appropriate electrical test methods. 1.4 This guide addresses those issues and concerns pertaining to irradiations with neutrons. 1.5 System and subsystem exposures and test methods are not included in this guide. 1.6 The range of interest for neutron fluence in displacement damage semiconductor testing ranges from approximately 109 to 1016 1-MeV (Si)-Eqv.-n/cm². 1.7 This guide does not address neutron-induced single or multiple neutron event effects (nSEE) or transient annealing. 1.8 This guide provides an alternative to Test Method 1017, Neutron Displacement Testing, a component of MIL-STD-883 and MIL-STD-750. 1.9
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use. 1.10
This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee. | File Size : | 1
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| Number of Pages : | 6 |
| Published : | 05/01/2024 |
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