DANSK DSF/PREN IEC 62433-6 PDF

The objective of this part of IEC 62433 standard is to describe the extraction flow for deriving an immunity macro-model of an Integrated Circuit (IC) against conducted Electrostatic Discharge (ESD) according to IEC 61000-4-2 and Electrical Fast Transients (EFT) according to IEC 61000- 4-4. The model addresses physical damages due to overvoltage, thermal damage and other failure modes. Functional failures can also be addressed. This model allows the immunity simulation of the IC in an application. This model is commonly called Integrated Circuit Immunity Model Conducted Pulse Immunity, ICIM-CPI. The described approach is suitable for modelling analogue, digital and mixed-signal ICs. Several terminals of an IC can be part of a single model (e.g. input, output and supply pins). The implementation of the model is capable of representing the non-linear behaviour of overvoltage protection circuits. The model can be implemented for the use in different software tools for circuit simulation in time-domain. The described modelling approach allows simulating device failure due to ESD or EFT at component and system level considering all components necessary for the immunity simulation of an IC, such as a PCB or external protection elements. This document demonstrates, in detail, the construction of models in a defined XML-based format which is suitable for the exchange of models without any deeper knowledge of the semiconductor circuit. However, the model functionality can be implemented in different formats including, but not limited to, tables, SPICE netlists, hardware description languages such as VHDL-AMS and Verilog-A.