Name:
IEC 62530 Ed. 3.0 en:2021 PDF
Published Date:
07/01/2021
Status:
Active
Publisher:
International Electrotechnical Commission
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
| Edition : | 3.0 |
| File Size : | 1 file , 16 MB |
| ISBN(s) : | 9782832299777 |
| Note : | This product is unavailable in Ukraine, Russia, Belarus |
| Number of Pages : | 1320 |
| Published : | 07/01/2021 |
