IEC/IEEE International Standard - Verilog(R) Register Transfer Level Synthesis

Publisher:
IEEE/IEC

Document status:

Active

Format:

Electronic (PDF)

Delivery time:

10 minutes

Delivery time (for Russian version):

200 business days

SKU:

- Inactive-Withdrawn. Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.

File Size :	1 file , 710 KB
ISBN(s) :	9780738147772
Note :	This product is unavailable in Russia, Belarus
Number of Pages :	116
Product Code(s) :	STDWD95358
Published :	12/18/2005

IEEE/IEC 62142-2005 PDF

IEC/IEEE International Standard - Verilog(R) Register Transfer Level Synthesis

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