Revision Standard - Active.
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (The PDF of this standard is available at no cost at https://ieeexplore.ieee.org/browse/standards/get-program/page compliments of Accellera Systems Initiative)
| ISBN(s) : | 9798855705010, 9798855712148, 9798855712155 |
| Note : | This product is unavailable in Russia, Ukraine, Belarus |
| Number of Pages : | 1354 |
| Product Code(s) : | STDRL26763, STDPD26763, STDPDRL26763 |
| Published : | 02/28/2024 |
