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JEDEC JEP147 PDF

JEDEC JEP147 PDF

Name:
JEDEC JEP147 PDF

Published Date:
10/01/2003

Status:
Active

Description:

PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
SKU:
Choose Document Language:
$15.9
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This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.
File Size : 1 file , 260 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 11
Published : 10/01/2003

History

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