JEDEC JEP150A PDF

The electronics industry has qualification standards for loose devices (e.g., JESD47, JESD94), printed wiring boards (PWBs) (e.g., IPC standards), and 2nd level interconnect reliability (i.e., solder joints) (e.g., IPC standards) that are performed as separate activities. This publication only addresses evaluating the intersection of how the stress state within a device may be altered once it is attached to a PWB, it does not address 2nd level interconnect reliability. This publication proposes a methodology on how to assess a device in package type whose stress state is susceptible to being altered once attached to a PWB. The severity or location of a failure mechanism and/or its time to failure may be altered from testing the device in the free standing state versus testing in the assembled state.

This publication contains a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products, that are in packages whose construction is such that when mounted to a PWB the stress state in the package may be significantly different from when stressed in a free-standing state. Such packages may include but are not limited to leadless chip carriers (e.g., OFN), ball grid array (BGA) packages, and packages with exposed pads that are attached to the PWB for thermal considerations. New package constructions should also be assessed as there does not exist historical knowledge of how the package stress state may be altered when tested in the assembled state. These could include fan out wafer level packages (FOWLP) and wafer level chip scale packages (WLCSP).

Assembled state testing may not be a prerequisite for device qualification; however, if the effect of assembly conditions on the device is not known, there could be reliability concerns for that device that are not evident in device level testing. Clause 4 describes the relationship between device level, PWB level, assembly level qualification testing in more detail and Clause 5 describes when assembly level qualification testing may be required. As such, it is recommended that assembly level testing be performed to determine if there are any adverse effects on that device due to its assembly to a PWB. Clause 8 provides guidance on the PWB to be used for the assembly level testing.

These reliability stress tests have been found capable of stimulating and precipitating failures in assembled devices in an accelerated manner, but these tests should not be used indiscriminately. Each qualification should be examined for:
a) Any potential new and unique failure mechanisms.
b) Any situation where these tests and/or conditions may induce false failures.

In either case the set of reliability requirements, tests and/or conditions should be appropriately modified to properly comprehend the new situations.

This document does not relieve the supplier of the responsibility to meet internal or customer specified qualification programs.