Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry.
| File Size : | 1
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| Note : | This product is unavailable in Ukraine, Russia, Belarus |
| Number of Pages : | 20 |
| Published : | 07/01/2014 |
