JEDEC JEP192 PDF

JEDEC JEP192 PDF

Name:
JEDEC JEP192 PDF

Published Date:
12/01/2022

Status:
Active

Description:

Guidelines for Gate Charge (QG) Test Method for SiC MOSFET

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

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For SiC MOSFET, the gate-charge characteristic behaves different to conventional silicon power MOSFETs. The most distinct point is the absence of a real Miller plateau. Due to short n-channels, which are typically used in SiC MOSFETs, practically a Miller “ramp” is measured. The standard QG extraction methods [1] cannot be easily applied. Furthermore, the presence of a VGS,TH hysteresis [2] makes it necessary to define clearly the starting gate voltage for QG measurement and extraction. The following document defines a QGS,TOT, QGD and QGS,TH which can be extracted from a measured QG waveform.

The test and extraction method can be applied to the following:
•N-Channel SiC MOSFET (vertical structure)
•Wafer and package levels


File Size : 1 file , 760 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 16
Published : 12/01/2022

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