JEDEC JESD 24-2 (R2002) PDF

JEDEC JESD 24-2 (R2002) PDF

Name:
JEDEC JESD 24-2 (R2002) PDF

Published Date:
01/01/1991

Status:
Active

Description:

ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

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Choose Document Language:
$15.9
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This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values.
File Size : 1 file , 160 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 11
Published : 01/01/1991

History


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