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JEDEC JESD 8-9B PDF

JEDEC JESD 8-9B PDF

Name:
JEDEC JESD 8-9B PDF

Published Date:
05/01/2002

Status:
Active

Description:

ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Czech version):
200 business days
SKU:
jedec-jesd-8-9b_1762702
Choose Document Language:
21.60 €
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This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.
File Size : 1 file , 180 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 28
Published : 05/01/2002

History

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