COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICES

Publisher:
JEDEC Solid State Technology Association

Document status:

Active

Format:

Electronic (PDF)

Delivery time:

10 minutes

Delivery time (for Russian version):

200 business days

SKU:

The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used.

File Size :	1 file , 54 KB
Note :	This product is unavailable in Ukraine, Russia, Belarus
Number of Pages :	14
Published :	09/01/2010

JEDEC JESD22-B108B PDF

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICES

History

Related products

Best-Selling Products