JEDEC JESD400-5C Document Release 1.3 PDF

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding.

All unused entries will be coded as 0x00. All unused bits in defined bytes will be coded as 0 except where noted.

Timing parameters in the SPD represent the operation of the module including all DRAMs and support devices at the lowest supported supply voltages (see SPD bytes 16 through 18), and are valid from tCKAVGmin to tCKAVGmax (see SPD bytes 20 through 23).

To allow for maximum flexibility as devices evolve, SPD fields described in this publication may support device configuration and timing options that are not included in the JEDEC DDR5 SDRAM data sheet (JESD79-5). Please refer to DRAM supplier data sheets or JESD79-5 to determine the compatibility of components.