JEDEC JESD8-33 PDF

Name:
JEDEC JESD8-33 PDF

Published Date:
06/01/2019

Status:
Active

Description:

.05 Low Voltage Swing Terminated Logic (LVSTL05)

Publisher:
JEDEC Solid State Technology Association

Document status:

Active

Format:

Electronic (PDF)

Delivery time:

10 minutes

Delivery time (for Russian version):

200 business days

SKU:

This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03

File Size :	1 file , 130 KB
Note :	This product is unavailable in Ukraine, Russia, Belarus
Number of Pages :	10
Published :	06/01/2019

History

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