JEDEC JESD8-6 PDF

Name:
JEDEC JESD8-6 PDF

Published Date:
08/01/1995

Status:
Active

Description:

ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

Publisher:
JEDEC Solid State Technology Association

Document status:

Active

Format:

Electronic (PDF)

Delivery time:

10 minutes

Delivery time (for Russian version):

200 business days

SKU:

This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz.

File Size :	1 file
Note :	This product is unavailable in Ukraine, Russia, Belarus
Number of Pages :	20
Published :	08/01/1995

History

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