ITU-T V.41 PDF

General

This Recommendation is primarily intended for error control when implemented as an intermediate equipment which may be provided either with data terminal equipment or with the data circuit-terminating equipment. The appropriate interfaces are shown in Figures 1/V.41 and 2/V.41. The system is not primarily intended for use with multiaccess computing systems. The Recommendation does not exclude the use of any other error-control system that may be better adapted to special needs.

The modems used must provide simultaneous forward and backward channels. The system uses synchronous transmission on the forward channel and asynchronous transmission on the backward channel. When modems to Recommendation V.23 are used with data signalling rates of 1200 or 600 bit/s in the general switched telephone network, Recommendation V.5 applies, the error-control equipment being classed as communication equipment. The margin of the synchronous receiver should be at least ± 45%.

The system employs block transmission of information in fixed units of 240, 480, 960 or 38401) bits and is therefore most suited to the transmission of medium or long data messages, but a fast starting procedure is incorporated to improve the transmission efficiency for shorter messages.

Error control is achieved by means of automatic repetition of a block upon request (ARQ) from the data receiver. If storage is provided at the receiver, detected errors can be removed before the system output (clean copy). Storage for at least two data blocks must be provided at the transmitter.

The forward bit stream is divided into blocks each consisting of four service bits, the information bits, and 16 error-detection (or check) bits in that order, the check bits being generated in a cyclic encoder. Thus each block transmitted to line contains 260, 500, 980 or 3860¹⁾ bits.

The system will detect:

a) all odd numbers of errors within a block;

b) any error burst not exceeding 16 bits in length and a large percentage of other error patterns.

Assuming a distribution of errors as recorded in reference [1], the error-rate improvement factor has been indicated by a computer simulation to be of the order of 50 000 for a block size of 260 bits.

The fixed block system employed limits the use of the system to those lines having a loop propagation time not greater than the figures given in Table 1/V.41. Allowances of 40 ms for total modem delay and 50 ms for the detection of the RQ signal have been made.

¹⁾ This block length is suitable for circuits provided by means of geostationary orbit satellites.