Publisher : JEDEC

DDR5 SDRAM

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DDR5 SDRAM

Document status: Active

1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

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SCALABLE LOW-VOLTAGE SIGNALING FOR 400 MV (SLVS-400)

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1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

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STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)

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BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V

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DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS

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FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

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POD18 - 1.8 V Pseudo Open Drain I/O

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