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JEDEC JESD8-15A PDF

JEDEC JESD8-15A PDF

Name:
JEDEC JESD8-15A PDF

Published Date:
09/01/2003

Status:
Active

Description:

STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
SKU:
Choose Document Language:
$18.6
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This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases.
File Size : 1 file , 290 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 21
Published : 09/01/2003

History

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