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IEC 62142 Ed. 1.0 en:2005 PDF

IEC 62142 Ed. 1.0 en:2005 PDF

Name:
IEC 62142 Ed. 1.0 en:2005 PDF

Published Date:
06/27/2005

Status:
[ Withdrawn ]

Description:

Verilog (R) register transfer level synthesis

Publisher:
International Electrotechnical Commission

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
SKU:
Choose Document Language:
$79.5
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Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
Edition : 1.0
File Size : 1 file , 750 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 109
Published : 06/27/2005

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