JEDEC JEP159 PDF

JEDEC JEP159 PDF

Name:
JEDEC JEP159 PDF

Published Date:
08/01/2010

Status:
Active

Description:

PROCEDURE FOR THE EVQLUQTION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

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$18.6
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This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back-end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis.
File Size : 1 file , 86 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 24
Published : 08/01/2010

History

JEDEC JEP159
Published Date: 08/01/2010
PROCEDURE FOR THE EVQLUQTION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY
$18.6

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