JEDEC JEP197 PDF

This guideline defines the evaluation method (measurement and stressing procedure) of on-state resistance increase or blocking current increase due to bipolar current stress in silicon carbide P/N diode-based devices. The guideline would be applicable to diodes, MOSFETs and any device sensitive to degradation due to electron hole recombination. This degradation mechanism will be termed ‘bipolar degradation’ in this publication.
Essentially, the bipolar degradation mechanism originates from conversion of pre-existing basal plane dislocations (BPDs) to stacking faults within the active drift region due to the recombination of electrons and holes in the current because of testing or stressing of the device. The direct effect of these stacking faults is an increase of on-state resistance or blocking current, thereby represents a degradation of the device’s properties. Section 7 is dedicated to a detailed description of this degradation mechanism.