JEDEC JESD 318 PDF

This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LPDDR5/5X SDRAM CAMM2s). These DDR5 and LPDDR5/5X CAMM2s are intended for use as main memory when installed in computers, laptops, and other systems.

“CAMM” is general language to describe the module category. CAMM2 is this JEDEC standard version while prior CAMMs have been proprietary.

Reference design examples are included which provide an initial basis for CAMM2 designs. Modifications to these reference designs may be required to meet all system timing, signal integrity and thermal requirements for PC5-6400, and beyond. CAMM2 with LPDDR5 DRAM is expected to start at 6400 MTs and increment upward in cadence with the DRAM speed capabilities. All CAMM2 implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design.

Related specifications:
• JESD79-5: DDR5 SDRAM specification
• JESD209-05A: LPDDR5 SDRAM specification
• JESD300-5: SPD5118 Hub and Serial Presence Detect Device Specification
• JESD301-2: PMIC5100 DDR Power Management Integrated Circuit (PMIC) Device Specification
• JESD301-3: PMIC52x0 LPDDR5/5X Power Management Integrated Circuit (PMIC) Device Specification
• JESD400-5: DDR Serial Presence Detect (SPD) Contents
• JESD406-5: LPDDR Serial Presence Detect (SPD) Contents
• JESD401-5: DDR5 DIMM Label
• JESD401-5: LPDDR5/5X DIMM Label
• JESD403-1: JEDEC Module Sideband Bus
• MO-210: Plastic Bottom Grid Array, 0.80 mm Pitch, Rectangular Family Package
• MO-338: 315-ball, pattern A CAMM2 Package