JEDEC JESD235B PDF

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 128 bit data bus operating at double data rate (DDR).

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Number of Pages :	207
Published :	11/01/2018