JEDEC JESD319 PDF

This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

This standard is intended to describe a baseline of standardized functionality and pinout that is focused on the CXL 3.1 based direct attached memory expansion application. It shall not be interpreted as prohibiting any additional functionality, innovations, or other types of value-adds or customizations implementors may choose to add above the specified baseline.

The standard describes unique identification for the requirements including the baseline attributes and defaults expected for ease of reference. The unique identification ID prefixed with REQ_* are stating requirements whereas prefix OPT_* are optional features.