JEDEC JESD47L PDF

JEDEC JESD47L PDF

Name:
JEDEC JESD47L PDF

Published Date:
12/01/2022

Status:
Active

Description:

Stress-Test-Driven Qualification of Integrated Circuits

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

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This standard describes a baseline set of acceptance tests for use in qualifying electronic devices as new products, a product family, or as products in a process which is being changed.

These tests are capable of stimulating and precipitating semiconductor device and packaging failure modes on free-standing devices not soldered to a printed wired board (PWB), or the like (base device reliability). The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs.


File Size : 1 file , 700 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 36
Published : 12/01/2022

History

JEDEC JESD47L
Published Date: 12/01/2022
Stress-Test-Driven Qualification of Integrated Circuits
Free Download
JEDEC JESD47K
Published Date: 08/01/2018
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
$22.8
JEDEC JESD47J.01
Published Date: 09/01/2017
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
$22.2
JEDEC JESD47J
Published Date: 08/01/2017
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
$22.2
JEDEC JESD47I
Published Date: 04/01/2011
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
$21.6
JEDEC JESD47H
Published Date: 02/01/2011
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
$20.1
JEDEC JESD 47G.01
Published Date: 04/01/2010
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
$20.1

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