JEDEC JESD8-4 PDF

JEDEC JESD8-4 PDF

Name:
JEDEC JESD8-4 PDF

Published Date:
11/01/1993

Status:
Active

Description:

ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

SKU:

Choose Document Language:
$14.4
Need Help?
This Addendum No. 4 to JEDEC Standard No. 8 defines the dc input and output specifications for a low-level, high-speed interface for integrated devices that can be a super-set of LVCMOS and LVTTL.
File Size : 1 file
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 8
Published : 11/01/1993

History


Related products

JEDEC JESD8-12A.01
Published Date: 09/01/2007
1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
$15.9
JEDEC JESD8-23
Published Date: 10/01/2009
UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS
$15.3
JEDEC JESD 8-9B
Published Date: 05/01/2002
ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
$21.6
JEDEC JESD8C.01
Published Date: 09/01/2007
INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS
$16.8

Best-Selling Products