JEDEC JESD8-8 PDF

Name:
JEDEC JESD8-8 PDF

Published Date:
08/01/1996

Status:
Active

Description:

ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

Publisher:
JEDEC Solid State Technology Association

Document status:

Active

Format:

Electronic (PDF)

Delivery time:

10 minutes

Delivery time (for Russian version):

200 business days

SKU:

This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.

File Size :	1 file , 1.2 MB
Note :	This product is unavailable in Ukraine, Russia, Belarus
Number of Pages :	18
Published :	08/01/1996

History

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