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JEDEC JESD82-16A PDF

JEDEC JESD82-16A PDF

Name:
JEDEC JESD82-16A PDF

Published Date:
05/01/2007

Status:
Active

Description:

DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
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Choose Document Language:
$24
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This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
File Size : 1 file , 350 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 43
Published : 05/01/2007

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