Revision Standard - Superseded.
The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language. (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).
| File Size : | 1
file
, 5.9 MB |
| ISBN(s) : | 9780738148519 |
| Note : | This product is unavailable in Russia, Belarus |
| Number of Pages : | 590 |
| Product Code(s) : | STDSU95395 |
| Published : | 04/07/2006 |
