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JEDEC JESD 36 PDF

JEDEC JESD 36 PDF

Name:
JEDEC JESD 36 PDF

Published Date:
06/01/1996

Status:
Active

Description:

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
SKU:
Choose Document Language:
$16.8
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This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.
File Size : 1 file , 43 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 15
Published : 06/01/1996

History

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