JEDEC JESD 78C PDF

JEDEC JESD 78C PDF

Name:
JEDEC JESD 78C PDF

Published Date:
09/01/2010

Status:
Active

Description:

IC LATCH-UP TEST

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Czech version):
200 business days

SKU:
jedec-jesd-78c_1779531

Choose Document Language:
21.60 €
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This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
File Size : 1 file , 190 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 28
Published : 09/01/2010

History

JEDEC JESD78F.02
Published Date: 11/01/2023
IC LATCH-UP TEST
JEDEC JESD78F.01
Published Date: 12/01/2022
IC LATCH-UP TEST
JEDEC JESD78F
Published Date: 01/01/2022
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JEDEC JESD78D
Published Date: 11/01/2011
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JEDEC JESD 78C
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IC LATCH-UP TEST
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JEDEC JESD 78B
Published Date: 12/01/2008
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