JEDEC JESD78D PDF

JEDEC JESD78D PDF

Name:
JEDEC JESD78D PDF

Published Date:
11/01/2011

Status:
Active

Description:

IC LATCH-UP TEST

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

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Choose Document Language:
$22.2
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This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
File Size : 1 file , 210 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 30
Published : 11/01/2011

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