Low prices! Originals & Translations! Save your budget and time!
ONLINENORMS: Online Standards Store
Click View Shopping Cart
  1. Home
  2. JEDEC
  3. JEDEC JESD 82-29A PDF

JEDEC JESD 82-29A PDF

JEDEC JESD 82-29A PDF

Name:
JEDEC JESD 82-29A PDF

Published Date:
12/01/2010

Status:
Active

Description:

DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
SKU:
Choose Document Language:
$34.8
Need Help?
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
File Size : 1 file , 640 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 80
Published : 12/01/2010

History

JEDEC JESD82-29A.01
JEDEC JESD82-29A.01
Published Date: 09/01/2022
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS
Free Download
JEDEC JESD 82-29A
JEDEC JESD 82-29A
Published Date: 12/01/2010
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS
$34.8

Related products

JEDEC JESD73
JEDEC JESD73
Published Date: 06/01/1999
DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS
$15.3
JEDEC JESD73-2
JEDEC JESD73-2
Published Date: 08/01/2001
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS
$15.3
JEDEC JESD76-2
JEDEC JESD76-2
Published Date: 06/01/2001
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION)
$14.4
JEDEC JESD82-18A
JEDEC JESD82-18A
Published Date: 01/01/2007
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERSFOR REGISTERED DDR2 DIMM APPLICATIONS
$18.6

Best-Selling Products

BS CISPR 12:1997
BS CISPR 12:1997
Published Date: 04/15/1999
Vehicles, motorboats and spark-ignited engine-driven devices. Radio disturbance characteristics. Limits and methods of measurement
$105.156
BS CISPR 16-1:1998
BS CISPR 16-1:1998
Published Date: 12/15/1998
Specification for radio disturbance and immunity measuring apparatus and methods-Radio disturbance and immunity measuring apparatus
$119.634
BS CISPR 16-1:1999
BS CISPR 16-1:1999
Published Date: 10/08/2003
Specification for radio disturbance and immunity measuring apparatus and methods-Radio disturbance and immunity measuring apparatus
$119.634
BS CISPR 16-2:1996
BS CISPR 16-2:1996
Published Date: 03/26/2003
Specification for radio disturbance and immunity measuring apparatus and methods-Methods of measurement of disturbances and immunity
$119.634
BS CISPR 16-3:2000
BS CISPR 16-3:2000
Published Date: 09/15/2000
Specification for radio disturbance and immunity measuring apparatus and methods-Reports and recommendations of CISPR
$119.634
CISPR 10 Amd.1 Ed. 4.0 b:1995
CISPR 10 Amd.1 Ed. 4.0 b:1995
Published Date: 04/28/1995
Amendment 1 - Organization, rules and procedures of the CISPR
$7.5