JEDEC JESD92 PDF

JEDEC JESD92 PDF

Name:
JEDEC JESD92 PDF

Published Date:
08/01/2003

Status:
Active

Description:

PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

SKU:

Choose Document Language:
$22.2
Need Help?
This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or "wear-out" of thin gate dielectrics used in integrated circuit technologies. The test is designed to obtain voltage and temperature acceleration parameters required to estimate oxide life at use conditions. The test procedure includes sophisticated techniques to detect breakdown in ultra-thin films that typically exhibit large tunneling currents and soft or noisy breakdown characteristics. This document includes an annex that discusses test structure design, methods to determine the oxide electric field in ultra-thin films, statistical models, extrapolation models, and example failure-rate calculations.
File Size : 1 file , 470 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 32
Published : 08/01/2003

History


Related products

JEDEC JESD28-A
Published Date: 12/01/2001
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS
$17.7
JEDEC JESD33-B
Published Date: 02/01/2004
STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE
$23.4
JEDEC JESD60A
Published Date: 09/01/2004
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
$20.1
JEDEC JESD61A.01
Published Date: 10/01/2007
ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE
$26.1

Best-Selling Products

Rigging Products Handbook
Published Date: 01/01/2002
$7.2