JEDEC JESD 35-A PDF

JEDEC JESD 35-A PDF

Name:
JEDEC JESD 35-A PDF

Published Date:
03/01/2010

Status:
Active

Description:

PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Russian version):
200 business days

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$26.1
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The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.
File Size : 1 file , 680 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 47
Published : 03/01/2010

History


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