JEDEC JESD22-B112A PDF

Name:
JEDEC JESD22-B112A PDF

Published Date:
10/01/2009

Status:
Active

Description:

PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE

Publisher:
JEDEC Solid State Technology Association

Document status:

Active

Format:

Electronic (PDF)

Delivery time:

10 minutes

Delivery time (for Russian version):

200 business days

SKU:

The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation.

File Size :	1 file , 1 MB
Note :	This product is unavailable in Ukraine, Russia, Belarus
Number of Pages :	30
Published :	10/01/2009

History

JEDEC JESD22-B112C

Published Date: 11/01/2023

Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature

Free Download

JEDEC JESD22-B112A

Published Date: 10/01/2009

PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE

$22.2

Related products

JEDEC JESD89-2A

Published Date: 10/01/2007

TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE

$18

JEDEC JS 9702

Published Date: 06/01/2004

IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)

$18

JEDEC JESD22-A111B

Published Date: 03/01/2018

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES

$18.6

JEDEC JESD22-B112A PDF

PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE

History

Related products

Best-Selling Products