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JEDEC JESD252 PDF

JEDEC JESD252 PDF

Name:
JEDEC JESD252 PDF

Published Date:
10/01/2018

Status:
Active

Description:

SERIAL FLASH RESET SIGNALING PROTOCOL

Publisher:
JEDEC Solid State Technology Association

Document status:
Active
Format:
Electronic (PDF)
Delivery time:
10 minutes
Delivery time (for Russian version):
200 business days
SKU:
Choose Document Language:
$15.9
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JEDEC JESD252 is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin.
File Size : 1 file , 160 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 12
Published : 10/01/2018

History

JEDEC JESD252.01
JEDEC JESD252.01
Published Date: 04/01/2021
Serial Flash Reset Signaling Protocol
$15.9
JEDEC JESD252
JEDEC JESD252
Published Date: 10/01/2018
SERIAL FLASH RESET SIGNALING PROTOCOL
$15.9

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