JEDEC JEP156 PDF

JEDEC JEP156 PDF

Name:
JEDEC JEP156 PDF

Published Date:
03/01/2009

Status:
Active

Description:

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

Publisher:
JEDEC Solid State Technology Association

Document status:
Active

Format:
Electronic (PDF)

Delivery time:
10 minutes

Delivery time (for Czech version):
200 business days

SKU:
jedec-jep156_1762510

Choose Document Language:
20.10 €
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This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
File Size : 1 file , 150 KB
Note : This product is unavailable in Ukraine, Russia, Belarus
Number of Pages : 24
Published : 03/01/2009

History

JEDEC JEP156A
Published Date: 03/01/2018
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
20.10 €
JEDEC JEP156
Published Date: 03/01/2009
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
20.10 €

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