JEDEC JESD22-B111A.01 PDF

The board level drop test method is intended to evaluate and compare drop performance of surface mount electronic components for handheld electronic product applications in an accelerated test environment, where excessive flexure of a circuit board causes product failure. The purpose of this document is to standardize the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components while duplicating the failure modes normally observed during product level test. This is not meant to replace any system level drop test that maybe needed to qualify a specific handheld electronic product nor to cover the drop test required to simulate shipping and handling related shock of electronic components or PCB assemblies. These requirements are already addressed in JESD22-B110.
The method is applicable to both area-array and perimeter-leaded surface mounted packages. The correlation between test and field conditions is not yet fully established. Consequently, the test procedure is presently more appropriate for relative component performance comparison than for use as a pass/fail criterion. Rather, results should be used to augment existing data or establish baseline for potential investigative efforts in package/board technologies.
The comparability between different test sites, data acquisition methods, and board manufacturers has not been fully demonstrated by existing data. As a result, if the data are to be used for direct comparison of component performance, matching study must first be performed to prove that the data are in fact comparable across different test sites and test conditions.
This method is not intended to substitute for full characterization testing, which might incorporate substantially larger sample sizes and increased number of drops. Due to limited sample size and number of drops specified here, it is possible that enough failure data may not be generated in every case to perform full statistical analysis.