ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES
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DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
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DEFINITION OF 'CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
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Definition of the SSTU32S869 and SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications
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Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications
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DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
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STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
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DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS
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DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS
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